During the manufacture of semiconductor technology, films of various materials are sequentially deposited and patterned on a semiconductor substrate such as a silicon substrate. For the back-end-of-line (BEOL) processing, these materials include metallization levels for the interconnect structures, dielectric levels used for insulation and capping, and barrier layers to prevent diffusion and oxidation of the interconnects. The current choice for interconnect metallization is copper, manufactured in a dual-damascene method. Dielectric materials include silicon oxide, deposited by plasma enhanced chemical vapor deposition (PECVD) using silane (SiH4) or tetraethylorthosilicate (TEOS) precursors, or organosilicate glass or borophosphosilicate glass (BPSG), deposited by chemical vapor deposition (CVD) for high-performance interconnect applications. The organosilicate glass can be in its dense form or in a form that includes porosity.
The choice of barrier layers includes tantalum, tantalum nitride, tungsten nitride ruthenium, iridium, and titanium and alloys of these metals.
As the critical dimension (CD) decreases, conformality and coverage problems from physical vapor deposition (PVD) techniques get worse for diffusion barrier and Cu plating seed depositions. These in turn will lead to fill issues during plating such as center and edge voids which cause reliability concerns and yield degradation. One way around this problem is to reduce the overall thickness of PVD material, and utilize a single layer of liner material which serves as both the diffusion barrier and plating seed. Another way around the aforementioned issue, is the use of chemical vapor deposition (CVD) or atomic layer deposition (ALD) which result in better step coverage and conformality as compared with conventional PVD techniques.
An example of such a material is Ruthenium (O. Chyan et al., “Electrodeposition of Copper Thin Film on Ruthenium: A Potential Diffusion Barrier for Copper Interconnects,” J. Electrochem. Soc., 150(5), p. C347, 2003). However, an issue that exists for the plating of Cu on Ru is the tendency of the Ru surface to oxidize on exposure to air which results in a decreased conductivity (and possibly adhesion) leading to poor plating. Apart from extremely poor fill of patterned structures, insufficient adhesion of Cu to surface oxide poses electromigration and stress reliability concerns. It has been suggested to address this problem by the use of process such a forming gas and hydrogen plasma exposures to reduce the surface oxide before plating. Drawbacks of these techniques include: 1) a time window (Queue time) exists within reduced wafers have to be plated before the surface oxide grows again, and 2) increased manufacturing cost due to required tooling for the reducing process, and increased raw process time.
A method that can eliminate or at least minimize plating voids inside an interconnect which is compatible with current plating tools and plating processes would be desirable.